The first part of this application example describes the generation of DTMF signals using the MSP430 microcontroller. An explanation is given of the most important specifications used in this case, the theoretical and mathematical justifications for generating sinusoidal signals using rectangular ones using appropriate analog filters are given. The example also includes tested demo programs for generating square wave signals based on various timer configurations on the MSP430 microcontrollers. The final part provides a circuit diagram that allows you to generate DTMF signals from rectangular signals.
2 Specification of DTMF signals
The abbreviation DTMF stands for “Dual Tone Multi Frequency” and is a method of representing digits with different frequencies in order to transmit them over analog communication lines, such as a telephone line. When developing the standard, the condition was taken into account - all frequencies should be in the "voice" range, which made it possible to reduce the requirements for the transmission channel. In telephone networks, DTMF signals are used to dial a number and convey other information. Despite the fact that the pulse dialing method, which is the standard, for example, in Germany, is still widely used, the dialing time is significantly increased, leading to unproductive loading of communication lines. In addition, many additional communication services are only possible using tone dialing. When encoded using the DTMF method, the numbers 0-9 and the letters A-D, */E and #/F are combinations of two frequencies:
| Frequency | 1209Hz | 1336Hz | 1477Hz | 1633Hz |
| 697Hz | 1 | 2 | 3 | A |
| 770Hz | 4 | 5 | 6 | B |
| 852Hz | 7 | 8 | 9 | C |
| 941Hz | */E | 0 | #/F | D |
In this system, the column represents the frequency from the "upper" frequency group (Hi-Group: 1209-1633 Hz) and the row represents the frequency from the "lower" frequency group (Lo-Group: 697-941 Hz). Tonal frequencies are chosen in such a way as to exclude the influence of harmonics. The frequencies are not multiples of each other and none of the DTMF frequencies can be obtained by summing or subtracting other frequencies. Dialing on the Deutsche Telekom network requires the following specifications to be met (taken from Zulassungsvorschrift des Bundesamtes fur Post und Telekommunikation, BAPT 223 ZV 5 (Official Specification of the Federal Ministry of Posts and Telecommunications):
3 Generating DTMF signals
As described above, DTMF signals are analog and consist of two independent sinusoidal signals. Thus, it is not possible to generate such signals only digitally. Digital signals must be converted using ADC and/or analog filters to the required sinusoidal form.
3.1 Generation with square wave signals
If square wave signals are used to generate DTMF signals, the software and hardware requirements are minimal. Any continuous signal having a period T can be represented by a Fourier series consisting of an infinite sum of sinusoids and cosine waves as follows:
Where a0/2 is the constant component of the signal. The sum element with the lowest angular frequency (w0) is called the fundamental (fundamental) harmonic, the rest are overtones or higher harmonics.
The simplest continuous signal implemented using a microcontroller is a meander, the Fourier series for which has the form:
The contribution of each of the frequency components to the total signal is best demonstrated by the amplitude spectrum (see Fig. 2):
Rice. 2: Amplitude spectrum of square wave
When using an analog filter, the DC component and higher harmonics are effectively suppressed, while at the output we have a sinusoidal signal with a frequency equal to the frequency of the original square wave.
3.2 Software for meander generation
The meander generation program must meet the following requirements:
- To be able to synthesize two independent rectangular signals.
- In order to separate signals, two output pins are required to generate signals from the “upper” (Hi-Group) and “lower” (Lo-Group) frequency ranges, respectively.
- The software must be able to set the desired duration of the signals in the range of approximately 65 ms - 100 ms.
The MSP430 series microcontrollers have various built-in timers capable of generating square wave signals. The '31x/'32x family uses an 8-bit timer and a Timer Port to generate both square wave signals. This program was tested at the MCLK frequency equal to 1.048 MHz. The Timer_A in the '33x family can independently generate both required signals. The second program uses this timer to generate meanders and works with any MCLK frequencies. Both programs will be discussed in detail below.
3.2.1 Square wave generation using 8-bit timer and Timer Port
On fig. 3 shows a block diagram of the initialization procedure for generating DTMF signals. To synthesize the two frequencies, the Timer Port and 8-bit timer counters are used. Each of them is a programmable counting register, necessary for the exact synthesis of the required frequencies. If the timer-port counters are cascaded into a single 16-bit timer and clocked from the MCLK system frequency, then high-band frequencies can be generated with high accuracy. When an interrupt occurs, the corresponding output is toggled and both 8-bit counter registers are reset. Loaded values are stored in two variables in RAM to save internal registers for other tasks.
The lower band frequencies are generated by an 8-bit timer. Since the counter register of this timer is 8 bits wide, only every third interrupt results in a level change on the required output pin, allowing the same counter to generate a frequency.
Two timer-port outputs are used to form two meanders of different frequencies.
Rice. 3 Flowchart of the initialization procedure for generating DTMF signals
The initialization procedure is executed only once. After its completion, the hexadecimal value of the transmitted character is read from the global variable into RAM. After the two frequencies that form the high and low DTMF tones are generated from the two tables, all that is required is initialization and start of both timers. The duration of the message is controlled by counting the half-cycles of the "lower" frequency and is read from an additional table. Upon completion of this procedure, you return to the polling function. The corresponding interrupt routines switch the port pins. This process is shown in Fig. 4 and 5.
The tasks of the timer-port include only fixing the log. level at the output of the port and reloading the counter from RAM, while the operation of an 8-bit timer has a slightly more complex structure: each input to the interrupt is counted by the counting register. The output can only change state after three interrupts. In addition, each half-cycle is also counted. Generation stops when a certain number of half-cycles is reached.
Rice. 4 Block diagram of interrupts from an 8-bit timer (Lo-Group)
Rice. 5 Block diagram of timer-port interrupts (Hi-Group)
; Custom definitions FLLMPY equ 32 ; 1.048 MHz FLL frequency multiplier TCLK equ FLLMPY*32768 ; TCLK: FLLMPY x f quartz DL equ 85 ; DTMF signal duration (65..100 ms) LO_OUT equ 02h ; Low frequency output HI_OUT equ 04h ; High frequency output RCOUNT equ r14 ; Length counter DTMF RTEMP equ r15 ; service register.global DTMF_NR ; global variable in RAM; for DTMF number (0..F) ; RAM definitions.even .bss DTMF_TL ; Even alignment.bss DTMF_TH .bss DTMF_NR ; global variable in RAM; for DTMF number (0..F) .even ; 8-bit timer definitions TCCTL EQU 42H TCPLD EQU 43H TCDAT EQU 44H ; Definitions for Generic Port Timer TPCTL equ 04bh ; Timer Port Control TPCNT1 equ 04ch ; Timer-Port Counter 1 TPCNT2 equ 04dh ; Timer Port Counter 2 TPD equ 04eh ; Timer Port Data TPE equ 04fh ; Permission timer-port.text ; DTMF frequency tables: table contains; number of MCLK cycles for one half cycle. ; Table for the "upper" frequency; Corrective amendment added; to take into account the time of entering the interrupt DTMF_HI .word 0ffffh-(TCLK/(1336*2))+25 ; High frequency for 0 .word 0ffffh-(TCLK/(1207*2))+28 ; High frequency for 1 .word 0ffffh-(TCLK/(1336*2))+25 ; High frequency for 2 .word 0ffffh-(TCLK/(1477*2))+24 ; Upper frequency for 3 word 0ffffh-(TCLK/(1207*2))+28 ; High frequency for 4 .word 0ffffh-(TCLK/(1336*2))+25 ; High frequency for 5 .word 0ffffh-(TCLK/(1477*2))+24 ; High frequency for 6 .word 0ffffh-(TCLK/(1207*2))+28 ; Upper frequency for 7 .word 0ffffh-(TCLK/(1336*2))+25 ; High frequency for 8 .word 0ffffh-(TCLK/(1477*2))+24 ; High frequency for 9 .word 0ffffh-(TCLK/(1633*2))+22 ; Upper frequency for A .word 0ffffh-(TCLK/(1633*2))+22 ; Upper frequency for B .word 0ffffh-(TCLK/(1633*2))+22 ; High frequency for C .word 0ffffh-(TCLK/(1633*2))+22 ; High frequency for D .word 0ffffh-(TCLK/(1207*2))+28 ; Upper frequency for * .word 0ffffh-(TCLK/(1477*2))+24 ; Upper frequency for # ; Table for "lower" frequency DTMF_LO .byte 0ffh-(TCLK/(941*2*3)) ; Low frequency for 0 .byte 0ffh-(TCLK/(697*2*3)) ; Low frequency for 1 .byte 0ffh-(TCLK/(697*2*3)) ; Low frequency for 2 .byte 0ffh-(TCLK/(697*2*3)) ; Low frequency for 3 .byte 0ffh-(TCLK/(770*2*3)) ; Low frequency for 4 .byte 0ffh-(TCLK/(770*2*3)) ; Low frequency for 5 .byte 0ffh-(TCLK/(770*2*3)) ; Low frequency for 6 .byte 0ffh-(TCLK/(853*2*3)) ; Low frequency for 7 .byte 0ffh-(TCLK/(853*2*3)) ; Low frequency for 8 .byte 0ffh-(TCLK/(853*2*3)) ; Low frequency for 9 .byte 0ffh-(TCLK/(697*2*3)) ; Low frequency for A .byte 0ffh-(TCLK/(770*2*3)) ; Low frequency for B .byte 0ffh-(TCLK/(853*2*3)) ; Low frequency for C .byte 0ffh-(TCLK/(941*2*3)) ; Low frequency for D .byte 0ffh-(TCLK/(941*2*3)) ; Low frequency for * .byte 0ffh-(TCLK/(941*2*3)) ; Low frequency for # ; Table of signal durations DTMF_L .byte 2*941*DL/1000 ; Half cycles for 0 .byte 2*697*DL/1000 ; Half cycles for 1 .byte 2*697*DL/1000 ; Half cycles for 2 .byte 2*697*DL/1000 ; Half cycles for 3 .byte 2*770*DL/1000 ; Half cycles for 4 .byte 2*770*DL/1000 ; Half cycles for 5 .byte 2*770*DL/1000 ; Half cycles for 6 .byte 2*852*DL/1000 ; Half cycles for 7 .byte 2*852*DL/1000 ; Half cycles for 8 .byte 2*852*DL/1000 ; Half cycles for 9 .byte 2*697*DL/1000 ; Half cycles for A .byte 2*770*DL/1000 ; Half cycles for B .byte 2*852*DL/1000 ; Half cycles for C .byte 2*941*DL/1000 ; Half cycles for D .byte 2*941*DL/1000 ; Half cycles for *.byte 2*941*DL/1000 ; Half cycles for # ;************************************************** ****************************** ; DTMF-TX DTMF subroutine ;************************************************ ******************************** DTMF_TX mov.b DTMF_NR,RTEMP ; Store number in temporary register mov.b DTMF_L(RTEMP),RCOUNT ; Save duration counter; prepare 8-bit timer for DTMF-Lo frequency mov.b #0a8h,&TCCTL ; Clock from MCLK mov.b DTMF_LO(RTEMP),&TCPLD ; Register preparation; preload mov.b #000,&TCDAT ; Loading the counter from the register; preload bis.b #008h,&IE1 ; Enable interrupts; from 8-bit timer; preparing timer-port for DTMF-Hi frequency rla r15 ; * 2 for 16-bit table mov DTMF_HI(RTEMP),&DTMF_TL ; save word for high frequency mov #003,RTEMP ; counter for 8-bit timer bis.b #008h,IE2 ; Enable interrupts; from timer-port mov.b &DTMF_TH,&TPCNT2 ; Load high byte into TC2 mov.b &DTMF_TL,&TPCNT1 ; Load low byte in TC1 bis.b #080h,&TPD ; Enable 16-bit timer bis.b #HI_OUT+LO_OUT,&TPE ; Enable DTMF-Hi/Lo outputs mov.b #090h,&TPCTL ; Enable timer ret ;************************************************** ****************************** ; Port timer interrupt;********************************************* ******************************* TP_INT xor.b #HI_OUT,&TPD ; DTMF-Hi output invert mov.b &DTMF_TH,&TPCNT2 ; Loading senior ba
3.2.2 1 Generating Square Waves Using Timer_A
This DTMF signal generation routine uses only the Timer_A timer to square off both desired frequencies. The assembly process calculates the appropriate values for the timer in order to use the program, regardless of the value of the MCLK frequency. The duration of the output signal is given by the constant DL in milliseconds.
; Hardware definitions; FLLMPY .equ 32 ; 1.048 MHz FLL Frequency Multiplier TCLK .equ FLLMPY*32768 ; TCLK: FLLMPY x f quartz DL .equ 82 ; DTMF signal duration in ms; (65..100ms) STACK .equ 600h ; Stack initialization address; Definitions of RAM; STDTMF .equ 202h ; Hi and Lo frequency status TIM32B .equ 204 ; Timer register extension LENGTH .equ 206h ; DTMF duration counter ; .text 0F000h ; Starting address of the program; ; Timer_A initialization: MCLK, Continuous mode, interrupts enabled; Preparing timer output modules Timer_A MCLK = 1.048 MHz (automatic) ; INIT MOV #STACK,SP ;Stack pointer initialization CALL #INITSR ;Multiplier initialization; FLL and RAM frequencies MOV #ISMCLK+TAIE+CLR,&TACTL ; Timer initialization MOV.B #TA2+TA1,&P3SEL ; Outputs TA2 and TA1 on ports P3.5/4 CLR TIM32B ; Clear extended BIS timer register #MCONT,&TACTL ; Start timer Timer_A EINT ; General interrupt enable MAINLOOP ... ; Main cycle; ;Key pressed: SDTMF contains table offset; for 2 frequencies (0..6,0..6) in high and low byte; MOV &TAR,R5 ; For immediate start: ADD FDTMFLO,R5 ; Offset for smaller time MOV R5,&CCR1 ; First state change in 0.71ms MOV R5,&CCR2 ; 1/(2x697) = 0.71ms MOV #OMT+CCIE,&CCTL1 ; Output invert, interrupt res. MOV #OMT+CCIE,&CCTL2 ; Invert output interrupt bit MOV.B STDTMF,R5 ; Counter for 82 ms RRA R5 ; number of low frequency state changes MOV.B DTMFL(R5),LENGTH ; for signal duration... ; continuation of the program; ; Interrupt handler from CCR0 (not used here) ; TIMMOD0 ... RETI ; ; Interrupt handler for capture-compare registers 1..4 ; TIM_HND ADD &TAIV,PC ; Processing the request with the highest; priority RETI ; no interrupt request: RETI JMP HCCR1 ; request from CCR1 (DTMF low frequency) JMP HCCR2 ; request from CCR2 (DTMF high frequency) JMP HCCR3 ; request from CCR3 JMP HCCR4 ; request from CCR4 ; TIMOVH INC TIM32B ; Timer_A extension to 32 bits RETI ; ; Low Frequency DTMF: TA1 inverts the output of the Output Unit 1 ; Each state change is counted to control the duration of the signal; HCCR1 PUSH R5 ; Save used registers MOV.B STDTMF,R5 ; DTMF low frequency status ADD FDTMFLO(R5),&CCR1 ; Add half cycle length DEC.B LENGTH ; DL signal duration completed? JNZ TARET ; No; ; Yes, stop issuing DTMF signal: disable interrupts; BIC #OMRS+OUT+CCIE,&CCTL1 ; Reset TA1 BIC #OMRS+OUT+CCIE,&CCTL2 ; Reset TA2 TARET POP R5 ; Restore R5 RETI ; Return from interrupt; ; High frequency DTMF: TA2 inverts the output of the Output Unit 2 ; HCCR2 PUSH R5 ; Saving used MOV registers. BSTDTMF+1,R5 ; DTMF high frequency status ADD FDTMFHI(R5),&CCR2 ; Add half cycle duration POP R5 ; Restore R5 RETI ; Return from interrupt; HCCR3 ... ;Task controlled by register CCR3 RETI HCCR4 ... ;Task controlled by register CCR4 RETI ; ; DTMF frequency table: the table contains; number of MCLK cycles per half cycle. Values adjusted for; the actual frequency MCLK during assembly; and rounded with the smallest possible frequency error; FDTMFLO .word ((TCLK/697)+1)/2 ; Lower frequency DTMF 697Hz .word ((TCLK/770)+1)/2 ; 770Hz .word ((TCLK/852)+1)/2 ; 852Hz .word ((TCLK/941)+1)/2 ; 941Hz FDTMFHI .word ((TCLK/1209)+1)/2 ; Upper frequency DTMF1209Hz .word ((TCLK/1336)+1)/2 ; 1336Hz .word ((TCLK/1477)+1)/2 ; 1477Hz .word ((TCLK/1633)+1)/2 ; 1633Hz ; The table contains the number of half cycles for the duration of the DL signal (ms). ; The lower DTMF frequency is used for counting; DTMFL .byte 2*697*DL/1000 ; Number of half cycles.byte 2*770*DL/1000 ; for DL in ms.byte 2*852*DL/1000 ; .byte 2*941*DL/1000 ; ; .sect "TIMVEC",0FFF0h ; Timer interrupt vectors Timer_A .word TIM_HND ; Module vector 1..4 timers.word TIMMOD0 ; Timer unit vector 0.sect "INITVEC",0FFFEh ; Reset vector Reset .word INIT
Below is a slightly faster solution. However, at the same time, it requires more RAM. the data received from the tables is not recalculated each time, but stored in two words in the RAM DTMFLO and DTMFHI. Reading is done from Timer_A interrupt routines. The tables used are identical to those in the previous example.
FLLMPY .equ 32 ; 1.048MHz FLL Frequency Multiplier TCLK .equ FLLMPY*32768 ; TCLK: FLLMPY x f quartz DL .equ 82 ; Duration of DTMF signal ; in ms (65..100 ms) STDTMF .equ 202h ; Hi and Lo frequency status TIM32B .equ 204 ; Timer register extension LENGTH .equ 206h ; DTMF duration counter DTMFLO .equ 208h ; Low frequency half cycle DTMFHI .equ 20Ah ; High frequency half cycle STACK .equ 600h ; Stack initialization address.text 0F000h ; Starting address of the program; Timer_A initialization: MCLK, Continuous mode, interrupts enabled; Preparing timer output modules Timer_A MCLK = 1.048 MHz (automatic) ; INIT MOV #STACK,SP ; Stack pointer initialization CALL #INITSR ; Multiplier initialization; FLL and RAM frequencies MOV #ISMCLK+TAIE+CLR,&TACTL ; Start timer MOV.B #TA2+TA1,&P3SEL ; Outputs TA2 and TA1 on ports P3.5/4 CLR TIM32B ; Clear BIS Timer Extended Register #MCONT,&TACTL ;Start Timer_A EINT ; General interrupt enable MAINLOOP ... ; Main Loop; Keystroke: SDTMF contains table offset; for 2 frequencies (0..6,0..6) in high and low byte; MOV &TAR,R5 ; For immediate start ADD FDTMFLO,R5 ; Offset for smaller time MOV R5,&CCR1 ; First state change in 0.71ms MOV R5,&CCR2 ; 1/(2x697) = 0.71ms; ; Fetch the two cycle counts for the DTMF frequencies ; MOV.BSTDTMF+1,R5 ; Upper frequency DTMF MOV FDTMFHI(R5),DTMFHI ; Half cycle duration MOV.B STDTMF,R5 ; Low frequency DTMF MOV DTMFLO(R5),DTMFLO ; The duration of the half-cycle; ; Duration counter RRA R5 ; Prepare byte index MOV.B DTMFL(R5),LENGTH ; number of low frequency state changes MOV #OMT+CCIE,&CCTL1 ; Output invert, interrupt res. MOV #OMT+CCIE,&CCTL2 ; Output invert, interrupt res. ... ; Return to the main loop; ; Interrupt handler from CCR0 (not used here) ; TIMMOD0 ... RETI ; ; Interrupt handler for capture-compare registers 1..4 ; TIM_HND ADD &TAIV,PC ; Processing the request with the highest; priority RETI ; no interrupt request: RETI JMP HCCR1 ; request from CCR1 (DTMF low frequency) JMP HCCR2 ; request from CCR2 (DTMF high frequency) JMP HCCR3 ; request from CCR3 JMP HCCR4 ; request from CCR4 ; TIMOVH INC TIM32B ; Timer_A extension to 32 bits RETI ; ; Low Frequency DTMF: TA1 inverts the output of the Output Unit 1 ; HCCR1 ADD DTMFLO,&CCR1 ; Add half cycle length DEC.B LENGTH ; DL signal duration completed? JNZ TARET ; No; ; Yes, stop issuing DTMF signal: disable interrupts; BIC #OMRS+OUT+CCIE,&CCTL1 ; Reset TA1 BIC #OMRS+OUT+CCIE,&CCTL2 ; Reset TA2 TARET RETI ; Return from interrupt; High frequency DTMF: TA2 inverts the output of the Output Unit 2 ; HCCR2 ADD DTMFHI,&CCR2 ; Add half-cycle length RETI ; Return from interrupt; HCCR3. .. ;Task controlled by register CCR3 RETI HCCR4 ... ;Task controlled by register CCR4 RETI ; ; Interrupt tables and vectors are identical to those shown in the previous example.
3.3 Hardware for generating DTMF signals
As mentioned above, in the frequency range 200 Hz.. 4600 Hz, the signal level of the transmission frequency must be at least 20 dB higher than the level of extraneous signals (noise). In addition, based on the specification, the signals from the "upper" and "lower" groups must have different levels, so each signal requires its own filter. The frequency amplitudes of the sinusoidal form can be obtained from the Fourier series.
To select cutoff frequencies when designing an analog filter, the following requirements must be adhered to, based on:
- Because it is necessary to ensure the possibility of any combination of the frequencies of the "lower" group with the frequencies of the "upper" group, the level difference between the lowest and highest frequency in the group should not exceed 3 dB.
- For the lowest frequency in the group (f1), the harmonic suppression (3f1) must be at least 20 dB. The fulfillment of this condition is most critical for the lower frequency in the group, since it is as far as possible from the cutoff frequency of the filter.
The formula describes the square of the absolute value at the output of the Butterworth high-pass filter of order n:
This formula represents the Butterworth high-pass filter gain as a function of frequency. The fg and n parameters determine the cutoff frequency and filter order, respectively.
First of all, it is necessary to calculate the required order of the filter, taking into account the compliance with the above requirements.
To fulfill the first condition, the ratio of the squares of the absolute values of the lowest and highest frequencies in the group must be no more than 3 dB, or:
The second condition will be fulfilled automatically if the ratio of the squares of the absolute values of the frequencies f1 and 3f1 is more than 10/3, in this case the third harmonic in a rectangular signal is 1/3 less (see the Fourier series and Fig. 2):
As a result of calculations for the frequencies of both groups, we have the required filter order n=1.15. Thus, a 2nd order filter, which can be built on an operational amplifier, will satisfy the requirements. In the case of using a 3rd order filter, only two additional elements are needed. However, this will reduce the requirements for component parameter spread. Both of the above requirements will be met if the cutoff frequency is within the following limits:
| bottom group | fg>880 Hz | fg<1418 Гц |
| Upper group | fg>1527 Hz | fg<2460 Гц |
If the cutoff frequency is at its minimum, maximum harmonic suppression will be observed. However, in this case, the difference between the levels of the lowest and highest frequencies in the group will be 3 dB. At the highest possible cutoff frequency, the level difference is minimal, but the harmonics are only reduced by 20 dB.
When calculating the filter, increased attention was paid to the suppression of harmonics, the level difference within the group was fixed at 2 dB. As a result, the cutoff frequencies are 977 Hz and 1695 Hz. The resulting harmonic suppression far exceeds the requirements. The difference in frequency levels in the group is within the requirements even in the case of the deviation of the cutoff frequency associated with the spread of the parameters of the components used. When calculating the values of the filter elements, the resistors were selected based on the consideration of their maximum proximity to the standard values of the E12 series.
At the filter outputs, the result is two sinusoidal signals with significantly suppressed harmonics. To combine these signals, an additional adder is introduced.
Thus, using only 3 op-amps and a few passive elements, we are able to generate DTMF signals using a microcontroller without using significant computing resources.
With the help of simulation programs, the approximate values were checked. The response of the filters very closely matches the calculated frequency response.
Rice. Figure 6: Amplitude spectrum of a 697 Hz square wave at the output of a 3rd order filter
On fig. Figure 6 shows the amplitude spectrum of a rectangular signal with a frequency of 697 Hz, passed through a 3rd order filter. As can be seen from the figure, the third and fifth harmonics (2091 Hz and 3485 Hz) are significantly attenuated (-25.6 dB).
Rice. Figure 7: Amplitude spectrum of a 941 Hz square wave at the output of a 3rd order filter
On fig. 7 shows the spectrum of a rectangular signal with a frequency of 941 Hz. In the frequency region of interest up to 4600 Hz, there is only one harmonic. After passing through the filter, this 2823 Hz harmonic is significantly attenuated (-27.9 dB). The level difference between the lowest and highest frequency in the group does not exceed 1.9 dB.
In order to use low-cost components with a high parameter spread, additional modeling was carried out. The simulation results showed that the allowable variation in the value of resistors and capacitors is 10%.
Fig 8: Histogram - distribution of signal levels in a group
Figure 9: Histogram - harmonic suppression
On fig. 8 and 9 show histograms obtained using Monte Carlo analysis. In this case, the values of the components changed randomly within a 10% spread. After 100 iterations, the results for all simulated filters are plotted on histograms. In the histogram in Fig. 8 shows the level difference between frequencies within a group. The maximum allowable difference of 3 dB between the minimum and maximum frequencies was not reached in any case. The average value is 1.6 dB, which is slightly better than the calculated value of 2 dB.
On fig. 9 shows the attenuation of harmonics for the "lower" frequency group. The required value of 20 dB is achieved in all cases, the average value is approximately 27 dB. In the worst case, the harmonic is suppressed by 24.2 dB.
The values calculated for the filter of the "lower" frequency group are also carried out for the filter of the "upper" frequency group.
Both filters have identical circuitry. The difference is only in the cutoff frequencies of the filters for the upper and lower frequency groups. R1 and C1 form the 1st order HPF. Because the input resistance of the circuit also depends on R1, the value of this element should not be too small; otherwise, the microcontroller outputs will be overloaded and the square waveform will be distorted. In this case, additional frequencies resulting from intermodulation distortion will be added to the signal, which will negatively affect the signal-to-noise ratio.
The transfer function of higher order filters cannot be obtained using only passive components.
Thus, the 2nd order filter must contain an operational amplifier. The gain of the active filter is set to 0.2 with resistors R1-1 and R1-2. As can be seen, the signal is somewhat attenuated in this case. This is necessary to avoid overloading the OS, because. the peak amplitude of the fundamental sinusoidal harmonic of the square wave exceeds the amplitude of the square wave proper (See Fourier series and Fig.2). In an additional adder, the required output level is adjusted. Due to the DC component of the square wave, the operating point of the op amp is set to Vcc/2 (See also the Fourier series and Fig. 2). In this case, the DC component cannot be eliminated by the input divider R1-1/R1-2. Capacitor C3 is used to decouple the OS circuit for DC voltage.
At each of the outputs of the analog filter, a signal of the upper and lower frequency groups is formed, respectively. In an additional adder, these signals are added. In this circuit element, you can set the ratio between the "lower" and "upper" frequencies in the total signal and the output signal level using resistors R4 and R5. Thus, the output amplitude can be easily adjusted according to different requirements in different countries.
When calculating the values of the components, the values of the capacitors were, as usual, fixed, and the values of the resistors were calculated in accordance with them. In this circuit, capacitors and resistors of the standard E12 series with a spread of 10% were used.
On fig. 10 shows the circuit diagram of the analog filters and adder:
Rice. 10: Schematic diagram of analog filters with additional adder
Capacitors C1-1 and C1-2 combine the two signals together at the operating point with the Vcc/2 level. For these elements, you should not choose too large values, because. they are elements of a low-pass filter to eliminate low-frequency subharmonics. Filter capacitor C5 eliminates voltage reference noise. An additional capacitor C6 connected in parallel to the feedback resistor R6 forms a first-order high-pass filter. If the lowest filter cutoff frequency is selected, the additional filtering of high-frequency intermodulation noise improves the quality of the output signal, however, there will be some attenuation of the highest frequencies of the “upper” group. In some cases, generating the highest DTMF frequency of 1633 Hz is not required because it is used only for the formation of service symbols A-D, while it is possible to improve the signal-to-noise ratio by lowering the filter cutoff frequency. Thus, increasing the cutoff frequency leads to an increase in the level of high-frequency interference, but at the same time, the negative effect on the highest frequency components of the DTMF signal is reduced.
4 Results of DTMF transmitter signal studies
The spectrograms below (Fig. 11 and 12) show the output signals of the DTMF transmitter at various frequencies. On fig. 11 shows the amplitude spectrum of the symbol “1”. The frequencies required for its transmission - 697 and 1207 Hz are at the level of -10.5 dB and -8.5 dB, respectively. Harmonics 2091 and 3621 Hz are suppressed by almost 30 dB. To transmit the “D” character, the two highest frequencies are generated - 941 and 1633 Hz. As can be seen from fig. 12, the lower frequency level is -12 dB, the upper frequency level is -11 dB. The corresponding harmonics are attenuated by more than 30 dB. Thus, the measured values correspond to the results of the simulation and the requirements of the specification.
Rice. 11: Amplitude spectrum of symbol “1”: 697 and 1207 Hz
Rice. 12: Amplitude spectrum of the “D” symbol: 941 and 1633 Hz
Absolute frequency accuracy of the generated square wave signals cannot be achieved when using two different timers, the result will depend on the combination of the two frequencies and the type of timers used. The reason for this is a timer interrupt conflict. However, the required accuracy of ±1.8% is met by a large margin.
If an 8-bit timer and a Timer Port timer at the system frequency MCLK 1.048 MHz are used, then the frequencies of the "lower" group are generated with an accuracy of no worse than 0.3%. For the frequencies of the "upper" group, in practice, the deviation is not higher than 0.5%.
The only exception is the DTMF character “D”, for which the highest frequencies are generated. As a result, in this combination, the frequency of the "upper" group of 1633 Hz has a deviation of -0.97%.
Without this exception, even the highest frequency of 1633 Hz is generated with better than 0.5% accuracy. The maximum deviations for various frequencies are given in the table:
If Timer_A is used to generate frequencies, the error will depend on the MCLK frequency used:
| MCLK, MHz | 1,048 | 2,096 | 3,144 | 3,800 |
| Multiplier FLL | 32 | 64 | 96 | 116 |
| 697 Hz | +0,027% | +0,027% | +0,027% | +0,027% |
| 770 Hz | -0,015% | -0,016% | +0,033% | -0,016% |
| 852 Hz | +0,059% | -0,023% | +0,005% | +0,031% |
| 941 Hz | +0,029% | +0,029% | +0,029% | +0,035% |
| 1209 Hz | -0,079% | +0,036% | +0,036% | -0,003% |
| 1336 Hz | +0,109% | -0,018% | +0,025% | +0,025% |
| 1447 Hz | -0,009% | -0,009% | -0,009% | -0,009% |
| 1633 Hz | +0,018% | +0,018% | +0,018% | +0,018% |
5 Conclusion
The software for this example is very simple and, taking up approximately 300 bytes, requires a small amount of RAM and ROM. Due to the built-in timer module, the required frequencies are generated with high accuracy without CPU overhead. In a configuration that uses an 8-bit timer and a Timer/Port for generation, the interrupt routines take up approximately 12% of the CPU resource. In the case when the frequencies are generated by the Timer_A timer, the CPU load for processing interrupt routines is reduced to 6%. As a result, other tasks may be performed during DTMF signaling, or the CPU may be put into low power mode to reduce current consumption.
The good functionality of the described module for generating DTMF signals using square wave signals is demonstrated by the hardware circuitry. Because in the circuit it is possible to use components with a large spread of parameters, the price of such a solution is very low. All specification requirements are met by a large margin, so a separate DTMF signal generator module is not required in instruments using the MSP430 as the master controller.
If in a particular case it is required to increase the signal-to-noise ratio, using an additional op-amp, a filter can be designed to further suppress intermodulation distortion. Such an additional operational amplifier is already present in the quad op-amp in the DIL14 package.
6 Links
Bundesamt fur Post und Telekommunikation (Federal Office for Post and Telecommunications): BAPT 223 ZV 5, Zulassungsvorschrift fur Endeinrichtungen zur Anschaltung an analoge Wahlanschlusse (ausgenommen Notruf- und Durchwahlanschlusse) des Telefonnetzes (official specification for terminals connected to analogue telephone lines , for except for security and calling requirements) / ISDN of the Deutschen Bundespost Telekom; Bundesministerium fur Post und Telekommunikation, Draft, Bonn April 1994 Papula: Mathematik fur Ingenieure 2 (Mathematics for Engineers); Vieweg Verlag, Braunschweig 1990 Tietze / Schenk: Halbleiterschaltungstechnik; (Tietze/Schenk, Semiconductor Circuitry), 10th.Edition; Springer Verlag, Berlin 1993 Lutz Bierl / Texas Instruments: MSP430 Family, Metering Application Report, Texas Instruments, Issue 2.1, Jan 1997, SLAAE10B Texas Instruments: MSP430 Family, Architecture User's Guide and Module Library, Texas Instruments, 1996, SLAUE10B Texas Instruments: MSP430 Family, Software User's Guide, Texas Instruments, 1996 Texas Instruments: MSP430 Family, Assembly Language Tools User's Guide, Texas Instruments, 1996 Siwy, Robert: Systementwicklung einer Telekom-Application zum Senden und Empfangen von DTMF-Signalen mit dem Microcontroller MSP430 (Development telecommunication system for receiving and transmitting digital signals based on the MSP430 microcontroller); Diplomarbeit, Fachhochschule Landshut, Mai 1997Distinctive features:
- Generation of sinusoidal signals using pulse-width modulation (PWM)
- Combining various sinusoidal signals into one DTMF signal
- Assembly and C source codes
- Designed to work with STK500
- Program code size 260 bytes / Constant table size 128 bytes
- Using the table conversion method
Introduction
This document describes how to generate DTMF (Dual Tone Multi-Frequency) signals using any AVR microcontroller containing a Pulse Width Modulation (PWM) block and SRAM. These signals are widely used in telephony, where they are played when you press the dialing buttons of the telephone set. To correctly generate a DTMF signal, two frequencies must be superimposed together: a low frequency (fb) and a high frequency (fa). Table 1 shows how different frequencies are mixed to produce DTMF tones when different keys are pressed.
Figure 1 - Scheme of the DTMF signal generator
Table 1 - Tone Shaping Matrix
| fb/fa | 1209 Hz | 1336 Hz | 1477 Hz | 1633 Hz |
| 697 Hz | 1 | 2 | 3 | A |
| 770 Hz | 4 | 5 | 6 | B |
| 852 Hz | 7 | 8 | 9 | C |
| 941 Hz | * | 0 | # | D |
The rows of Table 1 show low frequency values, while the columns show high frequency values. For example, the matrix shows that when you press the "5" button, the frequencies fb = 770 Hz and fa = 1336 Hz should be mixed. As a result of the addition of two sinusoidal signals of different frequencies, a DTMF signal is formed
where is the amplitude ratio K=Ab /Aa source signals must meet the condition
Operating principle
In addition to general information about the use of pulse-width modulation, the following will show how pulse-width modulation allows you to generate sinusoidal signals. The following paragraph describes how to obtain different frequencies using the base PWM frequency. After considering the theoretical foundations, a description of the DTMF signal generator itself will be given. Generation of sinusoidal signals
Depending on the ratio of the duration of the high VH and low VL voltage levels, the average value at the PWM output changes. If the ratio between the durations of both levels is kept constant, then a constant voltage level VAV will be generated as a result. Figure 2 shows a pulse width modulated signal.
Figure 2 - DC voltage level generation
The voltage level is determined by the expression:
(3)
A sinusoidal signal can be generated provided that the average value of the voltage generated by the pulse width modulation will change every PWM period. The ratio between high and low levels must be set according to the voltage level of the sinusoidal signal at the corresponding time. Figure 3 illustrates this process. The initial data for PWM are calculated for each of its periods and recorded in the conversion table (TP).
Figure 3 also illustrates the relationship between the frequency of the fundamental sine wave and the number of samples. The higher the number of samples (Nc), the higher the modeling accuracy of the resulting signal:
(4)
The PWM frequency depends on the PWM resolution. With 8-bit resolution, the end value (top of count) of the timer is 0xFF (255). Because timer counts up and down, this value must be doubled. Therefore, the PWM frequency can be calculated by dividing the timer clock frequency f CK by 510. Thus, with a timer clock frequency of 8 MHz, the resulting PWM frequency is 15.6 kHz.
Figure 3 - Generation of a sinusoidal signal using PWM
Changing the frequency of a sinusoidal signal
Assume that the sinusoidal samples are read from the lookup table not sequentially, but one at a time. In this case, at the same sample rate, a signal with a double frequency will be generated (see Figure 4).
Figure 4 - Doubling the resulting frequency (XSW = 2)
By analogy, if you read not every second value, but every third, fourth, fifth (respectively, the step width is 3, 4, 5 ...), etc. it is possible to generate Nc-frequencies in the range . Note that for high frequencies the resulting waveform will not be sinusoidal. We denote the step width according to the conversion table as X SW, Where
(5)
Calculation of the current position in the TP for the next PWM period (when the timer overflows) is performed using expression (6). New value in position X LUT depends on its previous state in position X" LUT with the addition of step width X SW
(6)
Adding different frequencies to get a DTMF signal
The DTMF signal can be generated using expressions (1) and (2). For simplicity of arithmetic operations, the value of the coefficient K is taken equal to 0.75 in order to replace the arithmetic operation with logical shifts. Taking into account expression (6), the current value for PWM control can be calculated by the expression:
and taking into account that X LUTa=X" LUTa + X SWa ,X LUTb=X" LUTb + X SWb, we finally write
Implementing a DTMF Generator
This appendix discusses building a DTMF tone generator using an 8-bit PWM output (OC1A) and a table of 128 sine function samples (Nc), each specified by 7 bits (n). The following expressions show this dependency and also show how to calculate the elements of the lookup table:
(9)
The advantage of using 7 bits is that the sum of the high and low frequency signal values is one byte in size. To support the full set of DTMF tones, 8 values for each DTMF frequency from Table 1 must be calculated and entered into a conversion table.
To achieve higher precision, the following solution was made: the values calculated by expression 5 require only 5 bytes. To use all 8 bytes, which will reduce the rounding error, this value is multiplied by 8. A pointer to the conversion table is written in the same way. But in this case, it takes two bytes to store 8 times the value. This means that 3 right shifts and an Nc base modulo operation (logical multiplication by Nc-1) must be performed before using these bytes as a pointer to sinusoid values in
Figure 5 - Scheme of the module for connecting to STK500
The PWM signal is generated at the OC1A (PD5) pin. An additional output filter will help to better match the sinusoidal waveform. As the PWM frequency decreases, it may be necessary to use a filter with a steeper frequency response to obtain a good result.
The connection of the keyboard is shown in Figure 1. The operation of the keyboard must be organized in such a way that it is possible to determine the pressed key. This can be done using the following algorithm:
- Determining the string of the pressed key
- set the lower tetrad of port B to the output and set the log. "0"
- configure the high tetrad of port B to the input with the connection of pull-up resistors
- the line with the pressed button is defined as the digit of the highest tetrad with a log. "0"
- Determining the key pressed column
- configure the senior tetrad of port B to the output and set the log. "0"
- set the lower tetrad of port B to the input with the connection of pull-up resistors
- the column with the pressed button is defined as the digit of the lowest tetrad with a log. "0"
Note: The STK200 has resistors in series between the PORTB connector pins and the microcontroller pins BP5, PB6, and PB7 (see the STK200 schematic). This will cause problems if a keyboard is connected to the PORTB connector.
Figure 6 illustrates the operation of the subroutine for determining the pressed key. Depending on the key pressed, the duration of the interval is determined. The interrupt routine uses this value to calculate the PWM settings for the two DTM tone sine waves. The interrupt handling procedure is shown in Figures 7 and 8.
This routine calculates a value to compare with the timer output for the next PWM period. The interrupt routine first calculates the position of the next sample value in the lookup table and reads the value stored there.
The position of the sample in the lookup table is determined by the pulse duration, and the actual pulse duration is determined by the generated frequency.
The final value, which is written to the timer comparison register, is determined using formula (7), which takes into account the sample values of both DTMF frequencies.
Figure 6 - Block diagram of the main program
With the introduction of modern digital exchanges in the telephone networks of the Russian Federation, a multi-frequency method for transmitting dialing signals, denoted by the English abbreviation DTMF (Dual-Tone Multiple-Frequency), is gradually spreading. Sometimes another English term is used to name this dialing signaling system - Touch-None (tone dialing). This method was developed in 1960, but its real distribution began in the 80s with the spread of digital (electronic) exchanges.
With this method of transmission of control signals, each multi-frequency signal of a digit of a number consists of two tones in accordance with the recommendation Q.23 ITU-T "Technical features of telephone sets with keypad dialing".
DTMF frequencies are not harmonized. This means that the frequencies do not have an integer divisor other than 1. For example, frequencies 1200 and 1600 Hz are harmonics of 400 Hz (3x400=1200 and 4x400=1600), and frequencies 697 and 770 Hz are non-harmonic.
Each signal contains two frequencies: one is selected from the lower, and the second - from the upper group of frequencies.
The correspondence between transmitted information and frequencies is given in the table on the front panel of the laboratory setup.
The transmission level in a two-frequency message, measured at a load of 600 Ohm, is: for the lower frequency group - minus 6dBmO ±2dB, for the upper frequency group - minus 3 dBmO ±2 dB. The frequency level of the upper frequency group in the total signal is 2 ±1 dB higher than the frequency level of the lower group. The sum level of all higher order frequency components is at least 20 dB below the lower group frequency level.
The conditions under which normal reception of signals should be carried out are as follows: the presence of two frequencies in the signal, one of which is selected from the lower group, and the other from the upper one; frequencies do not differ from their nominal values by more than 1.8%; the level of each of the two frequencies lies in the range from minus 7 to minus 30 dBmO; the difference between the levels of two frequencies does not exceed 3 dB; the duration of the frequency signal is at least 40 ms.
Perform the following operations before switching on the unit:
Switch S6 set to the lower position;
Switch S13 set to the upper position;
Set the switches of the generators of the upper and lower frequency groups to the "Off" position;
Set the analog key switch (AK) to the "On" position;
Turn the knobs for adjusting the output voltage of the generators and the resistor R3 counterclockwise until it stops.
Signal conditioning dtmf
1.1 Turn on the installation.
1.2 Connect the oscilloscope to the test point KT3.
1.3 Turn on the generator of the upper frequency group, by pressing one of the switch buttons, select any of the frequencies of this group.
1.4 Turning the generator output voltage adjustment knob, set the signal amplitude in KT3 equal to 0.5 Volts.
1.5 Switch the oscilloscope input to the control point KT4. Repeat steps 1.3, 1.4 for the generator of the lower frequency group by setting a voltage of 0.5 V in KT4.
NOTE: As a result of the performed operations, signals of the upper and lower frequency groups, equal in amplitude, were fed to the input of the adder. After setting these levels, fix the knobs for adjusting the output voltage of the generators.
1.6 Switch the oscilloscope input to the test point KT7. Turning the knob of the resistor (R3) for adjusting the output voltage of the DTMF signal conditioner, set the voltage in KT7 to 0.5 Volts.
NOTE: as a result of the operations performed, a continuous two-tone signal was applied to the input of the receiver, while the symbol corresponding to the combination of frequencies of the generators of the upper and lower frequency groups should be displayed on the indicator of the received symbol, in accordance with the table. An indication of the received and recognized signal is the presence of a signal at the STD output of the receiver (LED glow).
By switching the frequencies of the upper and lower frequency groups, make sure that the combinations of these frequencies correspond to the received symbols.
The invention relates to the field of generating digital methods of dual-tone frequency (DTMF) signals intended for data transmission, for example, in the field of telephony. Achievable technical result - reducing the number of redundant circuit elements, increasing economic efficiency. The DTMF signal generator, which implements the Method for generating DTMF signals, contains two accumulative adders, two holding registers, two memory devices, a final adder, a digital-to-analog converter, a converter of DTMF signal codes in a sequence of integers, a divider of the master frequency of the DTMF signal generator with an adjustable division ratio, a converter codes of DTMF signals into a division factor code. 2 s. and 3 z.p. f-ly, 2 ill.
The invention relates to methods for generating digital DTMF (two-tone frequency) signals intended for data transmission, for example, in the field of telephony with tone-frequency dialing. The closest in technical essence and the achieved result to the claimed method is the method for generating DTMF signals presented in US patent No. 5034977 dated 04.04.89, publ. 07/23/91, M.cl. 5 H 04 M 1/00. A known method for generating DTMF signals includes selecting the first and second sampling angle codes corresponding to the first and second frequency components of the DTMF signal, cumulative summation separately of the first and second sampling angle codes with respectively periodically fixed, with a period corresponding to the clock sampling frequency, the first and second results of the cumulative summation, obtaining the first and second discrete values of the DTMF signal components stored in the address cells of the corresponding tables of discrete values of the DTMF signal components by reading from the respective tables at the addresses corresponding to the results of the cumulative summation of the sampling angle codes, summing of the first and second discrete values of the components of the DTMF signal to obtain the third discrete value corresponding to the value of the DTMF signal. corresponding to the group of high frequencies - columns, and by means of the second conversion of DTMF codes of signals, the second code is selected, which determines the sampling angle of the signal with a frequency corresponding to the group of lower frequencies - rows, periodically, with a period corresponding to the sampling clock frequency, the first code of the sampling angle is summed in the corresponding cumulative adder and is fixed in the corresponding register, the output of which is the result, the value of which corresponds to the address of the table cell stored in the corresponding permanent memory and which contains the corresponding discrete values of the sines that determine the upper frequency of the DTMF signal in the same way, periodically, with a period, corresponding to the sampling clock frequency, the second code of the sampling angle is summed up in the corresponding accumulative adder and fixed in the corresponding register, at the output of which is the result, the value of which corresponds to the address of the table cell stored in the corresponding permanent memory and in which the corresponding discrete values of the sines that determine the lower the frequency of the DTMF signal, the discrete values of the sines that determine the upper and lower frequencies of the DTMF signal, are summed in the final adder, determining the discrete value of the DTMF signal, and are fed to the output through a digital-to-analog conversion, forming a step-sinusoidal DTMF signal corresponding to the input code of the DTMF signal. The known method is inefficient due to its low technical and economic indicators and technological indicators. Technical and economic indicators are determined by the necessary costs when implementing the method to achieve the necessary parameters for DTMF signals. In the known method, the accuracy of frequency generation depends on the bit depth of the code corresponding to the sampling angle, which requires a large bit length of the accumulative adder, which makes it difficult to implement the method with simple hardware. Namely, the sampling angle code in the known method is determined by the expression K=(F/F t)32..., (1.1) where K is the code corresponding to the sampling angle; F is the generated frequency; F t is the sampling frequency. As can be seen, the accuracy of the generated frequency uniquely depends on the ratio of the generated frequency and the sampling rate. To achieve the required accuracy of the generated frequency, namely, no worse than 1.5%, obviously, at least two significant digits after the decimal point are required, which requires data to be presented with a bit depth for lower frequencies of at least 8 bits, and for high frequencies at least 9 bits, and for cumulative summation, respectively, at least 12 bits, which leads to an increase in the number of components of devices that implement the known method. Known devices for implementing the known method, namely adders, registers, read-only memory devices have inputs/outputs with a capacity of 4 and 8 bits. Therefore, with a larger capacity, additional technical and economic costs are required for the implementation of equally functional devices. At the same time, in the known method, a decrease in the number of digits after the decimal point leads to a frequency error that exceeds the allowable one. Technological indicators are determined by universality and unification in the implementation of the method, for example, the state of the art, which implies a decrease in material consumption, component elements and an increase in the versatility of devices, requires the use of microcontrollers. Widespread microcontrollers used in telephony and telemetric measurements use 8-bit data and an 8-bit arithmetic logic unit, which requires additional computational operations associated with data summation with a capacity of more than 8 bits and analysis of the transfer signal when implementing the known method. which increases the number of commands and, accordingly, the clock frequency of the microcontroller, as well as the amount of RAM of the microcontroller, which leads to an increase in the cost of devices using the known method for generating DTMF signals. This conclusion is given when analyzing the application of the known method in a tone dialer based on microcontrollers manufactured by Atmel, Microchip tnc, etc. , as it has limitations when using the method, including as part of microcontrollers for general use, which is expressed in increased technical characteristics for microcontrollers, which reduces their versatility. The closest in technical essence and the achieved result to the claimed DTMF signal generator is the DTMF generator signals, presented in US patent No. 5034977 dated 04.04.89, publ. 07/23/91, M.cl. 5 H 04 M 1/00. The well-known DTMF signal generator includes: the first accumulative adder, the first latch register, the first storage device, the second accumulative adder, the second latch register, the second storage device, the final adder, the digital-to-analog converter, and the output of the first accumulative adder is connected with the input of the first fixing register, the output of the first fixing register is connected to the input of the first storage device, as well as to one of the inputs of the first accumulative adder, the output of the first storage device is connected to one of the inputs of the final adder, the output of the second accumulative adder is connected to the input of the second fixing register, the output of the second holding register is connected to the input of the second storage device, as well as to one of the inputs of the second storage adder, the output of the second storage device is connected to another input of the final adder, the output of the final adder is connected to the input of a digital-to-analog converter, the output of which is the output of the DTMF signal generator. Known the generator also contains the first converter of DTMF signals codes into the corresponding codes of sampling angles corresponding to the upper frequencies of the DTMF signal, the second converter of codes of DTMF signals into the corresponding codes of sampling angles corresponding to the lower frequencies of the DTMF signal, and the output of the first converter of codes of DTMF signals is connected to another input of the first storage adder, the output of the second DTMF code converter is connected to another input of the second accumulative adder, the inputs of the first and second DTMF code converters are inputs of the DTMF signal generator, and the clock inputs of the first and second latching registers are connected to each other and are the input of the sampling frequency of the DTMF signal generator . The well-known DTMF signal generator provides a low technical result due to an excessive number of circuit elements associated with different, as well as an excessive bit width of the same functional elements. In addition, the implementation of the well-known technical solution is effectively possible in the form of a separate integrated circuit, however, this requires the organization of specialized production, but given that DTMF signal generators are part of multifunctional devices (telephone sets with advanced capabilities, devices for transmitting telemetric information over telephone lines, etc.) which are currently implemented on the basis of universal microcontrollers, the production of separate microcircuits of DTMF signals is economically inefficient. a method with high technical and economic indicators due to a decrease in the bit depth of operations of the same type, high technological indicators, when implementing the method, both in circuit design with simple hardware, and as part of a multifunctional microcontroller, associated with repeatability, in the implementation, of the same functional elements. technical solution, the task is to create a DTMF signal generator, in which, by introducing new elements and making new connections, the technical result is increased, associated with a decrease in the number of redundant circuit elements, and, accordingly, the economic efficiency associated with the possibility of implementing the proposed technical solution by widely available means is increased. the fact that in the known method of generating DTMF signals, including the selection of the first and second codes of the sampling angles corresponding to the first and second frequencies of the components of the DTMF signal, the cumulative summation of the first and second codes of the sampling angles separately with, respectively, periodically fixed, with a period corresponding to the sampling clock frequency, the first and second results of the cumulative summation, obtaining the first and second discrete values of the DTMF signal components stored in the address cells of the corresponding tables of discrete values of the DTMF signal components by reading from the respective tables at the addresses corresponding to the results of the cumulative summation of the sampling angle codes, summing the first and second discrete values of the DTMF signal components to obtain the third discrete value corresponding to the value of the DTMF signal, what is new is that the first and second discrete values of the DTMF signal components stored in the addressable cells of the corresponding tables of discrete values of the DTMF signal components are obtained by reading from the corresponding tables at the addresses corresponding to the results of the cumulative summation, respectively, of the first and second sequences of integers, the average value of which corresponds to the codes of the sampling angles corresponding to the components of the DTMF signal. In addition, the average value of the sequence of integers that form the result of the cumulative summation can be the arithmetic mean of these numbers. In addition, the periodic fixation of the first and second results of the cumulative summation can be with a period corresponding to the sampling clock frequency, different for different DTMF signals. It is also solved by the fact that in the well-known DTMF signal generator, which includes the first storage adder, the first latching register, the first storage device, the second storage adder, the second latching register, the second storage device, the final adder, the digital-to-analog converter, and the output of the first storage adder is connected to the input of the first fixing register, the output of the first fixing register is connected to the input of the first storage device, as well as to one of the inputs of the first storage adder, the output of the first storage device is connected to one of the inputs of the final adder, the output of the second storage adder is connected to the input of the second fixing register, the output of the second latch register is connected to the input of the second storage device, as well as to one of the inputs of the second storage adder, the output of the second storage device is connected to another input of the final adder, the output of the final adder is connected to the input of a digital-to-analog converter, the output of which is the output of the DTMF signal generator, new, according to of the invention is that the DTMF signal generator additionally comprises a converter of DTMF signals codes in a sequence of integer numbers, a divider of the master frequency of the DTMF signal generator with an adjustable division ratio, a converter of codes of DTMF signals to a division ratio code, and the first output of the converter of codes of DTMF signals in a sequence of integers numbers is connected to another input of the first storage adder, the second output of the DTMF code converter of signals in the sequence of integers is connected to another input of the second storage adder, the output of the divider of the master frequency of the generator of DTMF signals with an adjustable division factor is connected to the clock input of the converter of codes of DTMF signals in the sequence of integers , as well as with the clock input of the first latching register and the clock input of the second latching register, the output of the converter of DTMF codes of signals to the code of the division ratio is connected to the input of the division factor setting of the divider of the master frequency of the DTMF signal generator, the input of the divider of the master frequency of the DTMF signal generator with an adjustable division ratio is by the input of the master frequency of the DTMF signal generator, the input of the DTMF signal code converter to the division ratio code is connected to the input of the DTMF signal code converter in the sequence of integers and is the input of the DTMF signal generator. In addition, the DTMF code converter in the sequence of integers can be made in the form of a controlled programmable storage device, the memory of which consists of memory areas corresponding to the number of DTMF signals, consisting of memory cells corresponding to the length of the sequence of integers, made so that in one half of the memory cell stores a number related to the first sequence of integers, and the other half of the memory cell stores a number related, respectively, to the other sequence of integers, which are the terms of the respective accumulative adders, and the control of the programmable memory device is made with the possibility of separate selection control memory area and a separate memory cell. New features of the method for generating DTMF signals and the DTMF signal generator, together with the known features of these objects, provide new technical properties of the objects, and, as a result of these properties, a new necessary technical result is provided. A causal relationship between a set of features of the proposed method and the achieved technical result is explained as follows. To reveal the essence of the proposed technical solution, the following calculations will be convenient: y(P)=sin(n) (1.2), where y(P) is the discrete value of the sine function;=wT=27F/Fr (1.3) - sampling angle, measured in radians; n - sequence number of the sample - sample; F t \u003d F OSC / kd - clock sampling frequency, where F OSC - device reference frequency; kd - adjustable division factor. Then = 2FК D / F OSC . (1.4) As is well known, the sine function is periodic with a period of 2. To convert the sampling angle from radians to relative units and get the sampling angle code, we divide the entire period into m parts, where m is a binary integer. Thus, we get one minimal discrete part of the period:=2/m. (1.5) Sampling angle code is the relative value of the sampling angle in accordance with one part of the period, namely, K=/=2F/F t:2P/m=Fm/F t. (1.6) For example, for generated frequencies of 1477 Hz and 697 Hz (corresponding to the DTMF code of the signal “3”), at m=64, and the clock frequency F t =32768 HzK 697 =1.36; K l477 =2.88. Obviously, for the binary display of the sampling angle code K 697 =1.36 in respectively 136 requires 8 bits (1281+640+320+160+81+40+20+10), and K 1477 =2.88 in respectively 288 requires 9 bits (2561+1280+640+321+ 160+80+40+ 20+10). In this case, cumulative summation, respectively, in binary representation requires 12 bits, which determined the above-described shortcomings of the known solution. The proposed technical solution defines, for example, the number 1.36 as the average value of a sequence of integers 1 and 2, namely 1.36=(1x+2y)/(x+y), where x and y are respectively the number of numbers 1 and 2 , periodically repeating with a period (x + y). for example, 1.36=1+0.36. The relative accuracy of such a replacement, in accordance with the expression (1.7)=К/Ц (1.7), increases with an increase in the integer part of the sampling angle code value. For example, for the generated frequency of 697 Hz, m=64, and the clock frequency F t =32768 Hz, the error of replacing K 697 =1.36 with the values of the numbers 1 and 2, respectively, is 36 and 32%. At the same time, if you increase the value of m= 256, then the error of replacing K 697 = 5.45 with the values of the numbers 5 and 6, respectively, decreases by 9 and 10%. In this case, the error of the generated frequency, for example, when replacing K 697 = 5.45 with the values of the numbers 5 and 6 with a repetition period, equal to 16, 5.45 \u003d (5x + 6y) / (x + y), where (x + y) \u003d 16. Solving the equation, we get x \u003d 9, y \u003d 7, i.e. out of sixteen operations of cumulative summation, term 5 is summed nine times and term 6 is summed seven times, while actually K 697 = 5.4375, substituting this value into expression (1.6) for m = 256, F t = 32768 Hz, we determine the actual calculated value of the generated frequency F=696 Hz, while the error was 0.1%. components of the above expressions, and, accordingly, reducing the capacity of devices that implement the proposed method, which leads to a decrease in hardware and energy costs in the implementation of the method, and to ensure high technological performance of the proposed method when used in multifunctional devices due to reduced technical requirements. The features of the claimed technical solution and the technical result achieved are explained as follows. which ensure the implementation of the method by circuit elements with the same bit depth not exceeding 8-bit, while there is no redundancy of elements necessary to solve several problems, for example, to fix the result of cumulative summation, and to address the corresponding storage device, the same number of bits is used, implemented not more than 8-bit register, which can be made by public means in the form of a single microcircuit or, in a microprocessor version, by a single memory cell. In addition, the implementation of storage adders can be made in the form of identical devices, with the same bit depth, in the form of publicly available adder microcircuits operating with 4-bit terms. Of course, it is understood that the numbers and, accordingly, the devices that form the above sequences of integers, the totality of which the corresponding codes of sampling angles may be with a different bit depth, but the most optimal, from the point of view of fulfilling the goals set by the claimed solution, are 4-bit numbers. commands of microcontrollers necessarily includes commands operating with 4-bit numbers - nibbles. hardware, and as part of multifunctional microcontrollers, which determines the high economic efficiency of the technical solution. The invention is illustrated by a drawing, where Fig. 1 shows a functional DTMF signal generator that implements a method for generating DTMF signals. The DTMF signal generator includes a converter 1 of DTMF signal codes in sequence integers, a divider 2 of the master frequency of the DTMF signal generator with an adjustable division ratio, a converter 3 of DTMF codes to a division factor code, the first accumulative adder 4, the first latching register 5, the first storage device 6, the second storage device 7, the second latching register 8, the second accumulative adder, the final adder 10, the digital-to-analog converter 11. The operation of the DTMF signal generator is illustrated by the example of the implementation of the method for generating DTMF signals. Previously, based on expressions (1.4, 1.6) and technical data, in particular, the master frequency of the device where the proposed method will be implemented, sequences of integers are calculated that determine the corresponding codes of sampling angles, and codes of division coefficients for the divider 2 of the master frequency of the DTMF signal generator with an adjustable division factor, which are recorded in the corresponding cells of the memory areas of the converter 1 of the DTMF codes in the sequence of integers and the converter 3 of the codes of the DTMF signals into the codes of the division coefficients, also pre-calculate the discrete values of the corresponding sine functions, the number of which is determined by the number of samples m, and write to the corresponding memory devices 6 and 7, when generating a DTMF signal, at the inputs of the converter 1 and the converter 3, which are the inputs of the generator, for a while action of the DTMF signal, the code of the generated DTMF signal will be set, the code that determines the division factor for divider 2 will be set at the output of converter 3, while at the output of divider 2 the sampling frequency will be set periodically, with a period corresponding to the sampling clock frequency, from the first output of converter 1 there will be the input of the first cumulative adder 4 will be binary numbers included in the first sequence of integers, and from the second output of the converter 1 will be fed to the input of the second cumulative adder 9 binary numbers included in the second sequence of integers corresponding to the components of the DTMF signal, the results of the cumulative summation are given from the outputs of the cumulative adders to the inputs of the respective latching registers 5 and 8, from the outputs of the latching registers 5 and 8, the results of the cumulative summation, with a period corresponding to the sampling clock frequency, are fed to other inputs of the respective cumulative adders 4 and 9, as well as to the inputs of the corresponding storage devices 6 and 7, by setting the addresses of the discrete values of the sines of the corresponding components of the DTMF signal, from the outputs of the memory devices 6 and 7, the discrete values of the corresponding components of the DTMF signal are fed to the corresponding inputs of the final adder 10, at the output of which a discrete binary DTMF signal is formed, which is fed to the input of the digital-to-analog converter 11, which outputs a stepped sinusoidal DTMF signal corresponding to the input code of the DTMF signal. Converter 1 codes DTMF signals in the sequence of integers (figure 1) can be made in the form shown in figure 2, where the converter codes DTMF signals in the sequence of integers includes a control device 12, a programmable memory device 13. The operation of the DTMF signal generator is illustrated further on a specific example of the implementation of the proposed method in a telephone tone-frequency dialer. Previously, based on expressions (1.4, 1.6) and technical data, sequences of integers are calculated that determine the corresponding codes of sampling angles, and codes of division coefficients for divider 2 of the master frequency of the DTMF signal generator with adjustable division ratio. Considering that the implementation of the method includes the same type of calculations, to illustrate the work in a specific example, the implementation of the method for generating a DTMF signal corresponding to pressing the “7” key as part of a tone-pulse dialer is given. As the master frequency of the generator, a quartz frequency is set, the most common in telephone technology, namely F OSC = 3579545 Hz. Pressing the “7” key corresponds to a DTMF signal with an upper (columns) frequency of 1209 Hz and a lower (rows) frequency of 852 Hz. Since the DTMF signal simultaneously transmits two frequencies, the division coefficients are calculated for the higher - upper frequency so that the corresponding sampling angle code in accordance with expression (1.6) is close to the maximum value - 16, which is implemented by no more than 4 bits data. Thus, at F OSC =3579545 Hz, the number of discrete values of sines m=128, the calculated values of the division factor for divider 2 of the master frequency of the DTMF signal generator with adjustable division factor K D =240=460, while the corresponding sampling angle codes for the upper frequency K 1209 /852 =10.376, for the lower frequency K 852/1209 =7.312. According to the invention, the sampling angle codes are replaced by sequences of integers, respectively, 10/11 and 7/8.10.375=(10x+11y)/(x+y), while actually K 1209 / 852 = 10.3757.312 = (7x + 8y) / (x + y), while in fact K 952/1209 = 7.313, with (x + y) = 16. Thus, 10.375 is replaced by periodically repeating sequence of integers 10 x 10 times and 11 x 6 times, and 7,312 is replaced as 7 x 11 times and 8 x 5 times. The memory area for the DTMF code of the “7” signal in binary representation is as follows: 
Thus, sixteen tables are calculated corresponding to the DTMF codes of signals, namely 0, 1, 2...9, *, #, A, B, C, D, and pre-recorded in the memory of the programmable storage device 13 (converter of the DTMF character code to sequence of integers). When a key is pressed, for example, “7” at the input of the generator for the duration of the DTMF signal, the binary code of the DTMF signal “7” (0111) is set, the converter 3 of the DTMF signal code into the division factor converts the DTMF signal code into the coefficient code division kd for the divider 2 of the master frequency generator with adjustable division ratio, the output of the divider 2 will be set to the sampling frequency F t =F OSC /K D . The DTMF code of the signal is also supplied to the address inputs of the high-order digits of the programmable storage device 13 (converter of DTMF signal codes to sequences of integers) and is present there for the duration of the DTMF signal. Controlled device 12, made, for example, in the form of a counter (converter of DTMF signals codes into sequences of integers), under the influence of clock signals with a frequency t, cyclically changes its value at the parallel outputs in series from 0000 to 1111, changing accordingly the values of the address inputs of the least significant digits of the programmable memory device 13 (converter codes DTMF signals in sequences of integers), at the output of the programmable memory device 13 with a clock sampling frequency appear 8-bit (byte) numbers, while in accordance with table 1, the highest four digits (highest nibble) form a sequence of integers , the set of which, namely, the arithmetic mean, determines the sampling angle code corresponding to the upper (columns) frequency, and the least significant four bits (lower nibble) form a sequence of integers, the set of which, namely, the arithmetic mean, determines the sampling angle code corresponding to lower (line) frequency, four-digit data, in accordance with table 1, from the output of the programmable storage device 13 (converter of DTMF signal codes to sequences of integers) are separately fed to the inputs of the respective storage adders 4 and 9, at the outputs of the respective adders 4 and 9 data change with a clock sampling rate from 0 to m (in this case, m=128), determining and fixing, by means of fixing registers 5 and 8, addresses for memory devices 6 and 7, into which binary discrete values of the corresponding sinusoidal components of the DTMF signal are respectively recorded, from the outputs memory devices 6 and 7, the binary discrete values of the corresponding sinusoidal components of the DTMF signal are fed to the corresponding inputs of the final adder 10, at the output of which binary discrete values of the DTMF signal are formed, which are then fed to the input of the digital-to-analog converter 11, at the output of which a stepped sinusoidal DTMF signal is formed. The DTMF signal generator can be implemented on the basis of well-known technical means, described, for example, in: The use of integrated circuits in electronic computing. Handbook / Ed. B.N. Faizulaeva, B.V. Tarabrin. - M.: Radio and communication, 1986. In this case, the converter 3 codes of DTMF signals into codes of division coefficients can be made, for example, in the form of a ROM chip 155PE 3 (p. 343), the implementation of the registers is described on p. 108, the implementation of accumulators is described on p. 114. The claimed method and the DTMF signal generator are also implemented on the basis of the technical means of Microchip Inc. (8-bit single-chip microcontrollers of the pic16f628 type), as part of the Kadran-NKT-01 pulse-tone telephone dialer manufactured by the Kadran company (Ukraine, Zaporozhye). The command system and the internal structure of the microcontroller nodes are described in: Prokopenko B.Ya. single chip microcontrollers. Dodeka, 2000, ISBN8-87835-056-4. A description of the DTMF signal parameters is given, for example, in: Integrated circuits: Microcircuits for telephony. Issue 1. - M.: Dodeka, 1994, 256 p. - ISBN-5-87835-003-3., p. 12, 13.
CLAIM
1. A method for generating two-tone frequency (DTMF) signals, including the selection of the first and second sampling angle codes corresponding to the first and second frequencies of the DTMF signal components, the cumulative summation separately of the first and second sampling angle codes with respectively periodically fixed periods corresponding to the sampling clock frequency, the first and the second results of the cumulative summation, obtaining the first and second discrete values of the DTMF signal components stored in the address cells of the corresponding tables of discrete values of the DTMF signal components by reading from the respective tables at the addresses corresponding to the results of the cumulative summation of the sampling angle codes, summing the first and second discrete values of the DTMF signal components to obtain the third discrete value corresponding to the value of the DTMF signal, characterized in that the first and second discrete values of the DTMF signal components stored in the addressable cells of the corresponding tables of discrete values of the DTMF signal components are obtained by reading from the corresponding tables at the addresses , corresponding to the results of the cumulative summation, respectively, of the first and second sequences of integers, the average value of which corresponds to the codes of the sampling angles corresponding to the components of the DTMF signal.2. The method according to claim 1, characterized in that the average value of the sequence of integers that form the result of the cumulative summation is the arithmetic mean of these numbers. The method according to claim 1, characterized in that the periodic recording of the first and second results of the cumulative summation is performed with a period corresponding to the sampling clock frequency, which is different for different DTMF signals. DTMF signal generator, including the first accumulative adder, the first latch register, the first storage device, the second accumulative adder, the second latch register, the second storage device, the final adder, the digital-to-analog converter, the output of the first accumulative adder is connected to the input of the first latch register, the output of the first latch register is connected to the input of the first storage device, as well as to one of the inputs of the first storage adder, the output of the first storage device is connected to one of the inputs of the final adder, the output of the second storage adder is connected to the input of the second fixing register, the output of the second fixing register is connected to the input of the second storage device, as well as with one of the inputs of the second storage adder, the output of the second storage device is connected to another input of the final adder, the output of the final adder is connected to the input of a digital-to-analog converter, the output of which is the output of the DTMF signal generator, characterized in that the DTMF signal generator additionally contains a converter codes of DTMF signals in a sequence of integer numbers, a divider of the driving frequency of the generator of DTMF signals with an adjustable division ratio, a converter of codes of DTMF signals into a code of a division factor, moreover, the first output of the converter of codes of DTMF signals in a sequence of integer numbers is connected to another input of the first accumulative adder, the second output of the converter codes of DTMF signals in the sequence of integers is connected to another input of the second storage adder, the output of the divider of the driving frequency of the generator of DTMF signals with an adjustable division ratio is connected to the clock input of the converter of codes of DTMF signals in the sequence of integers, as well as to the clock input of the first fixing register and the clock input of the second fixing register, the output of the converter of DTMF signals codes to the code of the division factor is connected to the input of the division factor setting of the divider of the master frequency of the DTMF signal generator, the input of the divider of the master frequency of the DTMF signal generator with an adjustable division factor is the input of the master frequency of the DTMF signal generator, the input of the DTMF code converter into the division factor code is connected to the input of the DTMF signal code converter in the sequence of integers and is the input of the DTMF signal generator. 5. The DTMF signal generator according to claim 4, characterized in that the converter of DTMF signal codes into a sequence of integers is made in the form of a controlled programmable storage device, the memory of which consists of memory areas corresponding to the number of DTMF signals, consisting of cells corresponding to the length of the sequence of integer numbers memory, designed so that one half of the memory cell stores a number related to the first sequence of integers, and the other half of the memory cell stores a number related respectively to another sequence of integers, which are the terms of the corresponding storage adders, and the control of the programmable storage device is performed with the possibility of separate control of the selection of a memory area and a separate memory cell.The topic of simple devices, I decided to assemble a DTMF signal generator on the same ATtiny2313. For those who don't know, DTMF (Dual-Tone Multi-Frequency) is a two-tone, multi-frequency analog signal used to dial a telephone number. Read Wikipedia.
The decision to assemble such a device was dictated by the desire to try to implement complex analog signals using a microcontroller. No practical application was planned for this device, but who can use such a device? Enjoy!
Source DTMF generator
Now let's see what we got.
The signal is generated using PWM and an RC circuit is used to give it the desired shape. As a result, after the RC chain, we get the following signal (button 6 is pressed):
Throughout the useful signal curve, we observe a high frequency comb (the frequency is higher than audible, so it will not create noise) - this is the work of the RC chain. You can make the line smoother by increasing the capacitance of the capacitor or the resistance of the resistor, but in this case the range of the useful signal will be significantly reduced.
We look at the signal spectrum and make sure that there are two separate frequencies (the PWM frequency has gone beyond the display area), so everything is fine - the device is working as it should.
Ready solutions
For the tasks of generating and decoding a DTMF signal, there are ready-made solutions. Here are a couple of datasheets for these microcircuits.
DTMF generator
- DTMF decoder
P.S. It's a pity there is no ADC in ATtiny2313 - it was also possible to get a DTMF decoder! But nothing, I will repeat on the mega, I will definitely attach it.
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